1. Field of the Invention
The invention relates to bussing in a computer system. More specifically, the invention relates to using PCI as a cable bus to expand the number of PCI slots available in a system.
2. Related Art
The peripheral component interconnect (PCI) bus is a high performance low latency I/O bus architected to minimize system cost. PCI has quickly gained wide acceptance in the computer industry. The PCI bus standard provides for a high bandwidth and a flexibility that is independent of new processor technologies and increased processor speed. At this time, computer system architects are primarily designing speed sensitive peripherals such as graphics accelerators and SCSI disk drive controllers to be utilized with the PCI bus.
The PCI specification is well defined. See particularly, PCI Local Bus Specification, rev. 2.0, Apr. 30, 1993. The specification reflects that PCI is capable of running at any frequency up to 33 MHz. This high level of possible throughput makes PCI an ideal choice for volume servers. Unfortunately, at such speed, the PCI bus can only support 3-4 slots along a single bus segment. This number of slots is unacceptably low for a practical application in the volume server market Some prior systems have addressed this problem by cascading PCI buses on the host mother board. Unfortunately, such cascading increases the cost of the basic system and still fails to provide a level of slot expansion necessary in volume servers. Moreover, such single chassis systems are not readily expandable as the user's needs change.
The possibility of bussing between multiple modular chassis implicates some unique problem in the context of PCI. Specifically, using available PCI to PCI bridges, it is necessary to synchronize the clock system wide. Because PCI does not require a standard host clock signal, phase lock loops cannot be employed to synchronize both sides of the bridge. The shear physical dimension of a multi-chassis system makes such synchronization of a single clock domain even more problematic. These problems necessitated custom design for circuits to provide out of chassis slot expansion.
Additionally, the PCI bus specification requires four active low, level sensitive interrupt pins for all slots supported and defines these interrupts' use as hardware shareable. That means that multiple PCI devices can drive the same interrupt line or that multiple PCI interrupt lines can be driven by different devices but may result in a single interrupt being generated to the system interrupt controller to be serviced by a shared interrupt driver. Thus, as the number of slots amongst which the interrupts must be shared increases, the resources and overhead required to resolve the source of the interrupt also increases as the number of sharing slots increases.
It is therefore desirable to provide an apparatus which allows PCI slot expansion without unnecessarily increasing the cost of the host system. Such apparatus should be forward and backward compatible, without requiring customization to each specific system. The performance of an expanded slot must be maintained at an acceptably high level, and the system should be readily expandable to meet the demands of increasing processor power. It is also desirable to develop a way to simplify the interrupts generated by such an expanded system.